An asynchronous circuit is a sequential digital circuit that operates without a global clock signal. Instead, an asynchronous circuit has autonomous components that are triggered by signals that indicate the completion of operations.
A multi-rail asynchronous circuit encodes data and spacer values using two or more signal rails. In such encodings, the data value represents actual binary data fed to the circuit, for example, a TRUE or a FALSE value. The spacer value is used to initialize the circuit to prepare it for accepting the next data value.
Multi-rail asynchronous circuits operate in two phases, alternating between data and spacer values. In the first phase, data values are applied at circuit inputs and data values appear at circuit outputs. The second phase is triggered by the completion of the first phase. In the second phase, spacer values are applied at circuit inputs. The second phase is completed when the spacer values have propagated to the outputs. Both phases operate by feeding the value (data or spacer) at the circuit inputs and waiting for that value to propagate through the circuit to the outputs.
The most common encoding type in asynchronous, multi-rail logic is dual-rail encoding. In dual-rail encoding, a digital signal is represented by two binary rails, which assume a total of four states, (0, 0), (0, 1), (1, 0) and (1, 1). In one scheme, the (0, 0) value represents the spacer word, the (0, 1) value represents the TRUE data value, whereas the (1, 0) value represents the FALSE data value. The value (1, 1) is commonly unused, except in a scheme where both positive level and negative level signals are supported.
A reason for encoding digital signals in multi-rail representations is to enable the detection of the propagation of data values from the circuit inputs to the circuit outputs. A completion mechanism detects that the operation of the circuit has completed. Circuits designed using multi-rail representations can thus exhibit asynchronous, data-dependent input to output delays. These types of circuits can increase the performance of digital systems by replacing the conventional synchronous, combinational logic circuits, the operation of which is based on an external timing reference, i.e. a clock signal. The period of the clock signal is determined by the so-called critical path, which represents an input to output path, which may be triggered by a real input vector that exhibits the largest possible delay.
Detecting completion requires a specific mechanism to be added to the multi-rail circuit, the operation of which depends on the circuit implementation of the multi-rail logic. There are two known completion schemes, namely, “strongly-indicating” and “weakly-indicating”. “Strongly-indicating” circuits only propagate data values at the outputs after all internal nodes have settled to their final values. “Weakly-indicating” circuit propagate data values at the outputs even if some of the internal nets have not yet assumed their final values. Spacer values are propagated in both types identically.
The majority of digital designs today are implemented using synchronous techniques, requiring the presence of external clock signals. The key advantage of asynchronous circuits is the possibility to exploit data-dependent, true, input-to-output delay indicated by the circuit itself. Asynchronous circuits have the potential for increasing performance and are immune to parametric and environmental variations, such as temperature variations, power supply voltage fluctuations and variability in fabrication characteristics of on-chip devices.
Multi-rail asynchronous circuits are known. Unfortunately, multi-rail asynchronous circuits have relatively high dynamic power consumption due to the combination of the two-phase operation discipline and the multi-rail encoding, which introduces redundancy, i.e., in a dual-rail architecture, the false nodes generate the opposite value of the true ones, thus more signal transitions are added. A circuit is monotonic when its mode of operation guarantees that for every operation of the circuit, all of the signal transitions are always unidirectional, not necessarily in the same direction, e.g., some are rising, others falling, but always in a predetermined way. This mode of operation is termed monotonic. Advantageously, such a circuit is free of signal glitches or hazards. On the other hand, the two phase operation implies that on average 50% of the circuit nodes switch value while processing data or a spacer word. Therefore, it would be desirable to reduce the power consumption associated with such circuits. That is, it would be desirable to reduce the power consumption associated with asynchronous, multi-rail circuits.